Flash memory cells have enjoyed recent commercial success due to their relatively low cost, the ease in erasing information stored in a flash memory array and their applications to bank check cards, credit cards, and the like. A flash memory cell which is recognized by the semiconductor industry as a standard has not yet emerged. Many types of flash memories exist which embody many different architectures. The programming, reading and erasing of cells can be generally described under one of the following architectures-NOR, AND, or NAND. Further, the programming mechanism of the flash memory cell typically involves Fowler-Nordheim tunneling through an energy barrier or electron injection over an energy barrier.
The array erase mechanism for Fowler-Nordheim cells can involve floating gate to channel, floating gate to drain or floating gate to source as the charge clearing path from the floating gate. The floating gate to drain or source path can prove deleterious to cell operation by destroying the tunnel oxide area located between the floating gate overlap and the drain/source region. On the other hand the tunnel oxide can also be destroyed through the programming mechanisms (e.g., programming a logic one or logic zero on the floating gate) of conventional Fowler-Nordheim flash cells. These programming mechanisms can include charge carrier paths between the floating gate and drain or alternatively between the floating gate and source. However, conventional cells do not include a programming operation involving a path between the channel and floating gate. Such an operation would be desirable from a standpoint of limiting tunnel oxide degradation due to the field re-distribution effect across the entire tunnel oxide region. Until now, a flash memory cell which allows uniform channel programming has not existed.